/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name          : stm32f10x_vector.c
* Author             : MCD Application Team
* Version            : V2.0.3
* Date               : 09/22/2008
* Description        : STM32F10x vector table for EWARM5.x toolchain.
*                      This module performs:
*                      - Set the initial SP
*                      - Set the initial PC == __iar_program_start,
*                      - Set the vector table entries with the exceptions ISR address,
*                      - Configure external SRAM mounted on STM3210E-EVAL board
*                       to be used as data memory (optional, to be enabled by user)
*                      After Reset the Cortex-M3 processor is in Thread mode,
*                      priority is Privileged, and the Stack is set to Main.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_it.h"
#include <iostm32f100xB.h>

/* Private typedef -----------------------------------------------------------*/
typedef void( *intfunc )( void );
typedef union { intfunc __fun; void * __ptr; } intvec_elem;

/* Private define ------------------------------------------------------------*/
/* Uncomment the following line if you need to use external SRAM mounted on
   STM3210E-EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
extern void __iar_program_start( void );
//int __low_level_init( void );
/* Private functions ---------------------------------------------------------*/

#pragma language=extended
#pragma segment="CSTACK"

//void __iar_program_start( void );

#pragma section = ".intvec"
#pragma location = ".intvec"
/* STM32F10x Vector Table entries */
const intvec_elem __vector_table[] =
{
	{ .__ptr = __sfe( "CSTACK" ) },
	__iar_program_start,
	NMIException,
	HardFaultException,
	MemManageException,
	BusFaultException,
	UsageFaultException,
	0, 0, 0, 0,            /* Reserved */
	SVCHandler,
	DebugMonitor,
	0,                      /* Reserved */
	PendSV_Handler,
	SysTick_Handler,
	WWDG_IRQHandler,
	PVD_IRQHandler,
	TAMPER_IRQHandler,
	RTC_IRQHandler,
	FLASH_IRQHandler,
	RCC_IRQHandler,
	EXTI0_IRQHandler,
	EXTI1_IRQHandler,
	EXTI2_IRQHandler,
	EXTI3_IRQHandler,
	EXTI4_IRQHandler,
	DMAChannel1_IRQHandler,
	DMAChannel2_IRQHandler,
	DMAChannel3_IRQHandler,
	DMAChannel4_IRQHandler,
	DMAChannel5_IRQHandler,
	DMAChannel6_IRQHandler,
	DMAChannel7_IRQHandler,
	ADC_IRQHandler,
	USB_HP_CAN_TX_IRQHandler,
	USB_LP_CAN_RX0_IRQHandler,
	CAN_RX1_IRQHandler,
	CAN_SCE_IRQHandler,
	EXTI9_5_IRQHandler,
	TIM1_BRK_IRQHandler,
	TIM1_UP_IRQHandler,
	TIM1_TRG_COM_IRQHandler,
	TIM1_CC_IRQHandler,
	TIM2_IRQHandler,
	TIM3_IRQHandler,
	TIM4_IRQHandler,
	I2C1_EV_IRQHandler,
	I2C1_ER_IRQHandler,
	I2C2_EV_IRQHandler,
	I2C2_ER_IRQHandler,
	SPI1_IRQHandler,
	SPI2_IRQHandler,
	USART1_IRQHandler,
	USART2_IRQHandler,
	USART3_IRQHandler,
	EXTI15_10_IRQHandler,
	RTCAlarm_IRQHandler,
	USBWakeUp_IRQHandler,
};
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
//
//int __low_level_init( void )
//{
//    unsigned int * src = __section_begin(".intvec");
//
////    LowLevelInit();
////	VTOR = 0x08000000;
//	RCC_CFGR = 0; //int 8 MHZ bez deliteley vo vse shini
//	RCC_APB2ENR_bit.USART1EN = 1;
//	RCC_APB2ENR_bit.IOPCEN   = 1;
//	RCC_APB2ENR_bit.IOPBEN   = 1;
//	RCC_APB2ENR_bit.IOPAEN   = 1;
//	RCC_APB2ENR_bit.SPI1EN   = 1;
//	//   RCC_APB1ENR_bit.TIM6EN   = 1;
//	//   RCC_APB1ENR_bit.TIM2EN   = 1;
//	RCC_APB1ENR_bit.TIM2EN   = 1;
//	RCC_APB2ENR_bit.AFIOEN     = 1;
//	RCC_APB1ENR_bit.PWREN = 1;
//	RCC_APB1ENR_bit.BKPEN = 1;
//
//
//	RCC_APB2RSTR_bit.USART1RST = 1;
//	RCC_APB2RSTR_bit.IOPCRST   = 1;
//	RCC_APB2RSTR_bit.IOPBRST   = 1;
//	RCC_APB2RSTR_bit.IOPARST   = 1;
//	RCC_APB2RSTR_bit.SPI1RST   = 1;
//	RCC_APB1RSTR_bit.TIM6RST   = 1;
//	RCC_APB2RSTR_bit.AFIORST   = 1;
//	RCC_APB2RSTR_bit.USART1RST = 0;
//	RCC_APB2RSTR_bit.IOPCRST   = 0;
//	RCC_APB2RSTR_bit.IOPBRST   = 0;
//	RCC_APB2RSTR_bit.IOPARST   = 0;
//	RCC_APB2RSTR_bit.SPI1RST   = 0;
//	RCC_APB1RSTR_bit.TIM6RST   = 0;
//	RCC_APB2RSTR_bit.AFIORST  = 0;
//
//    VTOR = ((unsigned int)(src)) | (0x0 << 7);
//
//    return 1; // if return 0, the data sections will not be initialized.
//}
